CY7C1161KV18 architecture equivalent, 18-mbit qdr ii sram four-word burst architecture.
* Configurations With Read Cycle Latency of 2.5 cycles: CY7C1161KV18 – 2 M x 8 CY7C1176KV18 – 2 M x 9 CY7C1163KV18 – .
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